Sequential logic
Sequential logic blocks generate the flip-flops in a design. There should be no other logic generated inside the sequential block. No delays should ever be coded into synthesizable logic, including the sequential logic block. The sequential block is always coded with nonblocking statements. There should never be any blocking statements.
The sequential block is an always block with the clock (and possibly an asynchronous reset) in the sensitivity list. The flip-flops are defined as shown using variable names: name_ff, name_nxt, possibly name_meta and name_sync, or possibly an input port. Flip-flops can be set or cleared with the asynchronous reset. They should not be initialized if not required.
Qt Creator 2.2.0 has a bug that I cannot drag to resize the layout
The solution is to use Qt Designer instead, which is also included in the installation. It can be invoked by executing "designer" in the qt command line.
- verilog.org
- verilog.net
- verilog.com and IEEE standard
- Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! (Cliff Cummings)
- Synthesizable Verilog Examples
- Verilog manual (CSCI320, Bucknell)
- Verilog and logic lectures(MIT, Nathan Ickes and Rex Min)
- Blocking/nonblocking assignments
01I don't use Symbols.py, but I use a more manageable and extensible XML file to manage repository.
02This is a sample block Dropcap.
03This is a sample block Dropcap.
In order to make this tutorial more general, I will not focus on official supported Xilinx or Avnet FPGA development boards, but a third party board instead. It's well known that EDK is a great tool for the supported boards which you just click through, but a nightmare for third party boards. In this tutorial, I will show you how to make EDK work smothly with non-supported FPGA boards.
Before start, we need to decide which bus to use, PLB or AXI. PLB bus has become deprecated, it supports up to the current Virtex6/Spartan6, but will be replaced by AXI bus for newer generation --- Virtex 7. If what you are doing is a new design, I suggest to build your system on AXI for easier upgrade in the future, for existing system, you may just stick with PLB bus. Unfrotuantely, when I start to write this tutorial, Xilinx EDK 13.1 doesn't provide Virtex 6 HX series with AXI bus support. Therefore, I have to use the PLB bus for the time being. I think Xilinx will update EDK to support AXI bus on the Virtex 6 HX series. A new tutorial for AXI bus might be written later.
Introduction
This article is written with the target to eliminate new learner's most frequent questions: what's the difference between blocking assignment and non-blocking assignment?
Blocking Assignment
always @(posedge clk) begin a = in; b = a; out = b; end
